/******************************************************************************
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 3
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
*
* Remarks:
*
*   Module to detect both rising and falling edge
*
* References:
*
******************************************************************************/

`default_nettype none


/*
//---------------------------------------------------------------------------
// Module: edge_detector
//
// Remarks:
//    module to catch both rising and falling edge of a signal
//---------------------------------------------------------------------------
*/

module edge_detector (
//========== INPUT ==========

	input wire clk,						// clock input
	input wire reset_n,					// reset, active low
	input wire data_in,					// data input, expected to be a single pulse

//========== OUTPUT ==========
	output wire pulse_out				// output a pulse when edge is detected
	
//========== IN/OUT ==========

);
	// input delay register
	reg data_in_d1;
	
	always @(posedge clk or negedge reset_n) begin
		if (!reset_n) begin
			data_in_d1 <= 0;
		end else begin
			data_in_d1 <= data_in;
		end 
	end 
	
	assign pulse_out = data_in ^ data_in_d1;
	
endmodule // edge_detector

`default_nettype wire
